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CASPOC
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CASPOC
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Developed at TNO, The Netherlands, Compare is design tool for identifying parasitic inductance in Power Electronics designs without the need for a field solver, but with the same accuracy as a field solver.


The development of Power Electronics in the direction of faster switching devices and more integrated and compactly designed circuits introduce modeling problems that are lying beyond the borders of conventional circuit theory. A theoretical sound modeling approach that combines a firm theoretical basis with the smallest possible complexity of the model is highly desirable. The main goal of this theme of research is to retain the lumped element feature of circuit theory instead of resorting to Finite Element methods and programs.

The advantages are:
  • resulting models facilitate a better understanding of the design because they expose the relation between dominating parasitic elements and design parameters;
  • resulting models allow for the use of circuit simulators as Caspoc, Saber and Spice for calculation of transient waveforms.
  • Theoretical basis for added parasitics: not by trial and error
  • Use of concept of partial inductances
  • Program for entry geometrical data of circuit
  • Automated generation of SABER-template

(c) 2009 Simulation Research
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